The invention relates to circuitry biasing a field effect transistor having a source or drain coupled to an input of an amplifier so as to ensure that the field effect transistor is maintained in its triode region despite large changes in an input signal on an input of the amplifier, and more particularly to circuitry that greatly reduces input offset voltage due to parasitic leakage currents in JFET gain switches in a resistive gain network of a programmable gain amplifier and maintains selected JFETs in their triode regions irrespective of changes in the amplifier input signal.
Various programmable gain amplifiers (also referred to as switchable gain amplifiers are known in the art. For example, U.S. Pat. No. 4,855,685 discloses a typical programmable gain amplifier. Leakage currents from JFET switches commonly used in programmable gain amplifiers cause errors that degrade the gain accuracy. FIG. 4 shows a block diagram of a programmable gain amplifier including a high gain operational amplifier 50. Its non-inverting input receives the input voltage V.sub.IN. The inverting input of amplifier 50 is connected by conductor 22 to an input of each of P-channel JFET switch circuits 30-1, 30-2 . . . 30-N. Each such JFET switch circuit connects a different feedback resistor junction of feedback resistors 24-1, 24-2 . . . 24-N to the inverting input 22, to thereby allow accurate setting the gain of the programmable gain amplifier if JFETs of the JFET switch circuits are maintained in their triode regions. A decoder circuit 58 responds to gain setting inputs 59 to determine which of the various JFET switch circuits 30-1 . . . 30-N are open and which are closed.
The JFET switch circuits 30-1 . . . 30-N must be biased so that when each is turned off its gate-to-channel PN junction is reverse biased beyond its pinch-off voltage. The JFET switch circuits also must be capable of operating at suitably high speed. The parasitic junction leakage currents of the JFET switch circuits influence the voltage on conductor 22 and thereby cause an input offset error in amplifier 50. An example of a switching circuit that might be used to implement the JFET switching circuits 30-1 . . . 30-N is shown in FIG. 5, but that switching circuit has very high parasitic gate-to-substrate leakage current, and would cause a high input offset voltage error in amplifier 50.